1. Technical Field
The present invention relates to a refresh apparatus for a semiconductor memory device and a refresh method thereof and, in particular, to a refresh apparatus for a semiconductor memory device and a refresh method thereof that can refresh a normal cell and a redundant cell by enabling a normal main wordline and a redundant main wordline in one test mode.
2. Description of the Related Art
In general, a static random access memory (SRAM) cell includes normal cells and redundant cells. When one of the normal cells has a defect, the defective normal cell is replaced by a redundant cell. When such a replacement is made, it is necessary to determine if the redundant cell replacing the defective normal cell has a defect itself. If the redundant cell is defective, the defective redundant cell is replaced by another redundant cell. To replace the cell having a defect with a redundant cell, both the normal cell and the redundant cell must be tested. However, because conventionally the normal cell and the redundant cell are individually tested (namely, tested by changing a test mode), test time is increased. Accordingly, to reduce the test time, the normal cell and the redundant cell are tested simultaneously in one test mode. However, the redundant cell cannot be refreshed in the test mode.
A conventional refresh apparatus for a semiconductor memory device having the aforementioned problem is described in detail with reference to FIG. 1. As shown in FIG. 1, the conventional refresh apparatus for a semiconductor memory device includes an address buffer 10, a refresh counter 20, an address controller 30, an address multiplexer 40, a wordline enable signal generator 50, a redundant predecoder 60, a normal predecoder 70, a redundant main wordline driver 80 and a normal main wordline driver 90.
The refresh counter 20 of the refresh apparatus refreshes the data in the memory device at periodic intervals such as, for example, every 64 milliseconds (ms) so that the dynamic random access memory (DRAM) cell can maintain the data stored therein. However, the refresh counter 20 is capable of refreshing only the normal cells. Accordingly, the normal cells are refreshed, but the redundant cells are not refreshed.
It is an object of the present invention to reduce a test time by simultaneously refreshing a normal cell and a redundant cell in one test mode.
According to a first aspect, a refresh apparatus for a semiconductor memory device may include an address multiplexer for generating a row address for performing a refresh operation in response to a refresh request signal, a redundant cell refresh signal generator for generating a redundant cell refresh signal in response to the refresh request signal and a test mode signal, and a wordline enable signal generator for generating a normal main wordline enable signal and a redundant main wordline enable signal in response to the redundant cell refresh signal in a redundant cell test mode. The refresh apparatus may also include a wordline driver circuit for simultaneously refreshing normal cell and the redundant cell by simultaneously driving a normal main wordline and a redundant main wordline in response to the row address, the redundant cell refresh signal, the normal main wordline enable signal and the redundant main wordline enable signal in the redundant cell test mode.
According to a second aspect, a refresh method of a semiconductor memory device may include generating a row address for performing a refresh operation in response to a refresh request signal, generating a redundant cell refresh signal in response to the refresh request signal and a test mode signal, and generating a normal main wordline enable signal and a redundant main wordline enable signal in response to the redundant cell refresh signal in a redundant cell test mode. The refresh method may also include simultaneously refreshing a normal cell and a redundant cell by simultaneously driving a normal main wordline and a redundant main wordline in response to the row address, the redundant cell refresh signal, the normal main wordline enable signal and the redundant main wordline enable signal in the redundant cell test mode.